Digital computer systems have a history of continually increasing the speed of the processors used in the system. As computer systems have migrated towards multiprocessor systems, sharing information between processors and memory systems has also generated a requirement for increased speed for the off-chip communication networks. Designers usually have more control over on-chip communication paths than for off-chip communication paths. Off-chip communication paths are longer, have higher noise, impedance mismatches, and have more discontinuities than on-chip communication paths. Since off-chip communication paths are of lower impedance, they require more current and thus more power to drive.
When using inter-chip high-speed signaling, noise and coupling between signal lines (crosstalk) affects signal quality. One way to alleviate the detrimental effects of noise and coupling is through the use of differential signaling. Differential signaling comprises sending a signal and its complement to a differential receiver. In this manner, noise and coupling affect both the signal and the complement equally. The differential receiver only senses the difference between the signal and its complement as the noise and coupling represent common mode signals. Therefore, differential signaling is resistant to the effects that noise and crosstalk have on signal quality. On the negative side, differential signaling increases pin count by a factor of two for each data line. The next best thing to differential signaling is pseudo-differential signaling. Pseudo-differential signaling comprises comparing a data signal to a reference voltage using a differential receiver or comparator.
When high speed data is transmitted between chips, the signal lines are characterized by their transmission line parameters. High speed signals are subject to reflections if the transmission lines are not terminated in an impedance that matches the transmission line characteristic impedance. Reflections may propagate back and forth between driver and receiver and reduce the margins when detecting signals at the receiver. Some form of termination is therefore usually required for all high-speed signals to control overshoot, undershoot, and increase signal quality. Typically, a Thevenin's resistance (equivalent resistance of the Thevenin's network equals characteristic impedance of transmission line) is used to terminate data lines allowing the use of higher valued resistors. Additionally, the Thevenin's network is used to establish a bias voltage between the power supply rails. In this configuration, the data signals will then swing around this Thevenin's equivalent bias voltage. When this method is used to terminate data signal lines, a reference voltage is necessary to bias a differential receiver that operates as a pseudo-differential receiver to detect data signals in the presence of noise and crosstalk.
The logic levels of driver side signals are determined by the positive and ground voltage potentials of the driver power supply. If the driver power supply has voltage variations that are unregulated, then the logic one and logic zero levels of the driver side signals will undergo similar variations. If the receiver is substantially remote from the driver such that its power supply voltage may undergo different variations from the driver side power supply, then additional variations will be added to any signal received in a receiver side terminator (e.g., Thevenin's network). These power supply variations will reduce noise margins if the reference has variations different from those on the received signals caused by the driver and receiver side power supply variations.
The popular technique of source-synchronous clocking is often used for high speed interface systems. With this technique, the transmitting device sends a clock with the data. The advantage of this approach is that the maximum performance is no longer computed form the clock-to-output delay, propagation delay, and set up times of the devices and the circuit board. Instead, the maximum performance is related to the maximum edge rate of the driver and the skew between the data signals and the clock signals. Using this technique, data may be transferred at a 1 Gbps rate (1-nsec bit period) even though the propagation delay from transmitter to receiver may exceed one nanosecond. If standard double-data rate (DDR) driving is utilized, data is launched on both the rising and falling edges of the clock. In this case, duty cycle symmetry of the clock as detected at the receiver becomes important since each edge of the clock is also used to recover the data at the receiving end of the data path. If the clock is asymmetrical, then it will affect the eye pattern of the data signals that the clock is used to detect.
As the frequency of the data and clock signals increase, the amount of skew between the data signals and the clock signal in a clock group becomes important. The delay of the transmission path may be several clock cycles. To accurately detect data and to align all of the data signals before sending to core logic in a receiving chip, the data signals are delayed relative to the clock until an optimum sampling time is achieved. This is ideally in the middle of the eye window of the data signals. Since the data signals are sampled with a clock, the amount of delay in the delay line in the data paths is relative to the clock signal. If environmental factors cause the delay of the delay line to vary, then accurately sampling the clock may be compromised or may cause errors.
There is, therefore, a need for circuitry to determine if the delay line has a predetermined delay range relative to the clock period and to adjust the delay increments of the delay line to keep the delay within the predetermined delay range.